Based on the UMC 28nm process, a two-stage CTLE equalizer based on TAS-TIS structure and feedforward path is designed. The first stage CTLE adopts a transconductance cascade transimpedance (TAS-TIS) structure, which adopts active inductance as load, source-stage negative feedback network and transimpedance amplifier based on inverter unit, etc., which can effectively expand the circuit operating frequency without additional power consumption. The second stage CTLE adds a feed-forward path between the input transistor and the inductor, and the circuit increases the gain lift of the circuit without affecting the gain of the low frequency. The simulation results show that the eye width of the 40Gbps PAM4 (four-level pulse amplitude modulation) signal, 50Gbps PAM4 signal and 28Gbps NRZ (non-return-to-zero code) signal after equalization reaches 0.68/0.5/0.92 code element intervals (UI), respectively, which can meet the input signal requirements of the post-stage circuit.