Aiming at the requirement of low jitter in optical communication system, a high-speed clock data recovery circuit (CDR) was proposed. CDR employed a mixer-based phase detector (PD) to avoid the CK-to-Q delay of D flip-flop, achieved high operation speed and low jitter performance. The CDR also employed a frequency detection loop to improve the capture range, and no external reference was requeried. For high-speed application, some sub-circuits adopted inductive peaking technology, which improves the bandwidth performance effectively. The CDR circuit is designed in 45 nm CMOS process. The results show that the peak to peak jitter of the recovered clock and data is 2.19 ps and 2.32 ps respectively, the phase noise of clock is -101.4 dBc/Hz, the power consumption is 50.28 mW at 1 V supply.