1.School of physics and technology,Wuhan University,Wuhan,430072;2.P.R.China
针对光通信系统中对信号低抖动的要求,提出了一种高速时钟数据恢复电路(CDR)。CDR采用了混频器型线性鉴相器,避免了D触发器的时钟到输出延迟,在提升工作速率的同时取得了低抖动；CDR中还包括无参考时钟的鉴频环路,提升了捕获范围。为了高速应用,部分电路模块采用了电感峰化技术,有效提升了其带宽性能。该CDR电路在45 nm CMOS工艺下设计,仿真结果显示,CDR恢复出的时钟与数据的峰峰值抖动分别为2.19 ps和2.32 ps,时钟相位噪声-101.4 dBc/Hz,在1 V的电源电压下,功耗为50.28 mW。
Aiming at the requirement of low jitter in optical communication system, a high-speed clock data recovery circuit (CDR) was proposed. CDR employed a mixer-based phase detector (PD) to avoid the CK-to-Q delay of D flip-flop, achieved high operation speed and low jitter performance. The CDR also employed a frequency detection loop to improve the capture range, and no external reference was requeried. For high-speed application, some sub-circuits adopted inductive peaking technology, which improves the bandwidth performance effectively. The CDR circuit is designed in 45 nm CMOS process. The results show that the peak to peak jitter of the recovered clock and data is 2.19 ps and 2.32 ps respectively, the phase noise of clock is -101.4 dBc/Hz, the power consumption is 50.28 mW at 1 V supply.