On-chip integrated digitization is one of the main development directions of the infrared focal plane array, and its key technology is the integration of analog-to-digital conversion ADC blocks in the readout circuit. In response to the digitization requirements of the line linear InGaAs focal plane, a non-binary redundant bit SAR ADC design is adopted in this paper. The entire readout circuit includes a readout circuit unit and an analog-to-digital conversion unit. The readout circuit unit adopts the structure of CTIA, which has good structural linearity and high injection efficiency. The analog-to-digital conversion unit uses a SAR ADC, which has a simple structure and low power consumption. In this paper, the CDAC module is designed using a non-binary calibration method. In this paper, the CDAC module is designed using a non-binary calibration method. Which inserting redundant bits in the capacitor array to increase the conversion speed and accuracy of the ADC, and the sampling accuracy is improved using the bottom plate sampling technique. A 14-bit SAR ADC was designed and simulated with 0.18μm CMOS process model. At a sampling rate of 1MSPS, the SNR is 74dB and the ENOB is 13.4bits