In this paper, a high resolution, low power column level 14bit ADC for CMOS image sensor is proposed. The ADC is based on the RAMP ADC which is widely used in CMOS image sensor column circuits. The ADC adopts the two-step structure of 3-bit SAR ADC and 11-bit RAMP ADC, which reduces the quantization time by about 2/3. In the RAMP ADC part, the high-low clock counting method is adopted to reduce the power consumption in the counting part by about 90%. The correlated double sampling logic of RAMP-SAR-RAMP switch is proposed, which can reduce the amount of SRAM by about 40% and significantly reduce the layout area. In this paper, the 0.18μm standard CMOS process is employed, and the simulation is based on Cadence software. Under the working mode of 600MHz clock and single edge counting, the quantization time of ADC is 9.32μs, and the average power consumption in the counting part is about 8.51μW under the 1.8V digital power supply.