A self-adjustable CMOS charge pump phase-locked loop (CPLL) circuit with accelerated compensation for high-speed image sensors is designed. Regarding to traditional PLL topology, a "dual-mode" logical clock-controlled and low-power accelerated charging compensation module is added to achieve synchronize optimization in locking time and power consumption. Based on the 180nm/1.8V CMOS process, the circuit design and performance simulation are implemented. The results show that, based on the proposed acceleration compensation scheme, the improved PLL can meet the requirements of high-speed image sensoring application with low noise, low power and high frequency. When a reference signal of 1GHz is input, the proposed voltage-controlled ring-oscillator reaches 0.55~2.82GHz with 2.27GHz frequency range, phase noise is -98.149dBc/Hz@1MHz, locking time is shortened to 5.2μs, average power consumption is only 1.98mW, and the jitter noise in output can be as low as 2.81μV/Hz@1MHz. The proposed PLL has significant superior circuit in power and locking time compared with some other design cases.